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1/18 august 2002 M48T128Y m48t128v* 5.0 or 3.3v, 1 mbit (128 kb x 8) timekeeper ? sram * contact local st sales office for availability of 3.3v version. features summary n integrated, ultra low power sram, real time clock, power-fail control circuit, battery, and crystal n bcd coded year, month, day, date, hours, minutes, and seconds n automatic power-fail chip deselect and write protection n write protect voltages (v pfd = power-fail deselect voltage): C M48T128Y: v cc = 4.5 to 5.5v 4.1v v pfd 4.5v C m48t128v*: v cc =3.0to3.6v 2.7v v pfd 3.0v n conventional sram operation; unlimited write cycles n software controlled clock calibration for high accuracy applications n 10 years of data retention and clock operation in the absence of power n self-contained battery and crystal in the dip package n pin and function compatible with jedec standard 128k x 8 srams figure 1. 32-pin pmdip module pmdip32 (pm) module 32 1
M48T128Y, m48t128v 2/18 table of contents summarydescription...........................................................3 logicdiagram(figure2.).........................................................3 signalnames(table1.)..........................................................3 dip connections (figure 3.) .......................................................3 blockdiagram(figure4.).........................................................4 maximumrating.................................................................4 absolutemaximumratings(table2.) ...............................................4 dc and ac parameters. . ........................................................5 operating and ac measurement conditions (table 3.) ..................................5 ac testing load circuit (figure 5.) ..................................................5 capacitance (table 4.) . . . ........................................................5 dccharacteristics(table5.) ......................................................6 operationmodes...............................................................6 operating modes (table 6.) ........................................................6 readmode....................................................................7 readmodeacwaveforms(figure6.)..............................................7 readmodeaccharacteristics(table7.)............................................7 writemode...................................................................8 write enable controlled, write ac waveform (figure 7.) ..............................8 chipenablecontrolled,writeacwaveforms(figure8.)...............................8 writemodeaccharacteristics(table8.) ...........................................9 dataretentionmode............................................................10 powerdown/upmodeacwaveforms(figure9.) .....................................10 powerdown/upaccharacteristics(table9.)........................................10 powerdown/uptrippointsdccharacteristics(table10.)..............................11 clockoperations.............................................................11 reading the clock . .............................................................11 settingtheclock...............................................................11 registermap(table11.).........................................................12 stopping and starting the oscillator ................................................11 calibratingtheclock............................................................12 crystalaccuracyacrosstemperature(figure10.) ....................................13 clockcalibration(figure11.) .....................................................13 v cc noise and negative going transients . ..........................................14 supplyvoltageprotection(figure12.)..............................................14 partnumbering ...............................................................15 package mechanical information . . . ..........................................16 revisionhistory...............................................................17
3/18 M48T128Y, m48t128v summary description the M48T128Y/v timekeeper ? ram is a 128kb x 8 non-volatile static ram and real time clock. the special dip package provides a fully in- tegrated battery back-up memory and real time clock solution. the M48T128Y/v directly replaces industry standard 128kb x 8 sram. it also provides the non-volatility of flash without any requirement for special write timing or limi- tations on the number of writes that can be per- formed. the 32-pin, 600mil dip hybrid houses a controller chip, sram, quartz crystal, and a long life lithium button cell in a single package. figure 2. logic diagram table 1. signal names figure 3. dip connections ai02244 17 a0-a16 dq0-dq7 v cc M48T128Y m48t128v g v ss 8 e w a0-a16 address inputs dq0-dq7 data inputs / outputs e chip enable g output enable w write enable v cc supply voltage v ss ground nc not connected internally a1 a0 dq0 a7 a4 a3 a2 a6 a5 a13 a10 a8 a9 dq7 a15 a11 g e dq5 dq1 dq2 dq3 v ss dq4 dq6 a16 nc v cc ai02245 M48T128Y m48t128v 10 1 2 5 6 7 8 9 11 12 13 14 15 16 30 29 26 25 24 23 22 21 20 19 18 17 a12 a14 w nc 3 4 28 27 32 31
M48T128Y, m48t128v 4/18 figure 4. block diagram maximum rating stressingthedeviceabovetheratinglistedinthe absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 2. absolute maximum ratings note: 1. soldering temperature not to exceed 260c for 10 seconds (total thermal budget not to exceed 150c for longer than 30 seconds). caution: negative undershoots below C0.3v are not allowed on any pin while in the battery back-up mode. ai01804 lithium cell oscillator and clock chain v pfd v cc v ss 32,768 hz crystal voltage sense and switching circuitry 8 x 8 timekeeper registers 131,064 x 8 sram array a0-a16 dq0-dq7 e w g power symbol parameter value unit t a ambient operating temperature 0 to 70 c t stg storage temperature (v cc off, oscillator off) C40 to 85 c t sld (1) lead solder temperature for 10 seconds 260 c v io input or output voltages C0.3 to 7 v v cc supply voltage M48T128Y C0.3 to 7 v m48t128v C0.3 to 4.6 i o output current 20 ma p d power dissipation 1 w
5/18 M48T128Y, m48t128v dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 3. operating and ac measurement conditions note: output hi-z is defined as the point where data is no longer driven. figure 5. ac testing load circuit note: 50pf for m48t128v. table 4. capacitance note: 1. effective capacitance measured with power supply at 5v. sampled only, not 100% tested. 2. at 25c, f = 1mhz. 3. outputs deselected. parameter M48T128Y m48t128v unit supply voltage (v cc ) 4.5 to 5.5 3.0 to 3.6 v ambient operating temperature (t a ) 0 to 70 0 to 70 c load capacitance (c l ) 100 50 pf input rise and fall times 5 5ns input pulse voltages 0 to 3 0 to 3 v input and output timing ref. voltages 1.5 1.5 v ai03630 c l = 100pf or 50pf (1) c l includes jig capacitance 650 w device under test 1.75v symbol parameter (1,2) min max unit c in input capacitance 20 pf c io (3) input / output capacitance 20 pf
M48T128Y, m48t128v 6/18 table 5. dc characteristics note: 1. valid for ambient operating temperature: t a =0to70c;v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. outputs deselected. operation modes figure 4, page 4 illustrates the static memory array and the quartz controlled clock oscillator. the clock locations contain the year, month, date, day, hour, minute, and second in 24 hour bcd format. corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automatically. byte 1fff8h is the clock control register. this byte controls user access to the clock information and also stores the clock calibration setting. the seven clock bytes (1ffffh - 1fff8h) are not the actual clock counters, they are memory locations consist- ing of biport? read/write memory cells within the static ram array. the M48T128Y/v in- cludes a clock control circuit which updates the clock bytes with current information once per sec- ond. the information can be accessed by the user in the same manner as any other location in the static memory array. the M48T128Y/v also has its own power-fail detect circuit. this control circuitry constantly monitors the supply voltage for an out of tolerance condition. when v cc is out of toler- ance, the circuit write protects the timekeeper ? register data and external sram, providing data security in the midst of unpredictable system oper- ation. as v cc falls below the battery back-up switchover voltage (v so ), the control circuitry au- tomatically switches to the battery, maintaining data and clock operation until valid power is re- stored. table 6. operating modes note: x = v ih or v il ;v so = battery back-up switchover voltage. 1. see table 10, page 11 for details. symbol parameter test condition (1) M48T128Y m48t128v unit C70 C85 min max min max i li input leakage current 0v v in v cc 2 2 a i lo (2) output leakage current 0v v out v cc 2 2 a i cc supply current outputs open 95 50 ma i cc1 supply current (standby) ttl e =v ih 84ma i cc2 supply current (standby) cmos e =v cc C 0.2v 43ma v il input low voltage C0.3 0.8 C0.3 0.4 v v ih input high voltage 2.2 v cc +0.3 2.2 v cc + 0.3 v v ol output low voltage i ol = 2.1ma 0.4 0.4 v v oh output high voltage i oh = C1ma 2.4 2.2 v mode v cc e g w dq0-dq7 power deselect 4.5 to 5.5v or 3.0 to 3.6v v ih x x high z standby write v il x v il d in active read v il v il v ih d out active read v il v ih v ih high z active deselect v so to v pfd (min) (1) x x x high z cmos standby deselect v so (1) x x x high z battery back-up mode
7/18 M48T128Y, m48t128v read mode the M48T128Y/v is in the read mode whenever w (write enable) is high and e (chip enable) is low. the unique address specified by the 17 ad- dress inputs defines which one of the 131,072 bytes of data is to be accessed. valid data will be available at the data i/o pins within t avqv (address access time) after the last address input signal is stable, providing the e and g access times are also satisfied. if the e and g access times are not met, valid data will be avail- able after the latter of the chip enable access times (t elqv ) or output enable access time (t glqv ). the state of the eight three-state data i/o signals is controlled by e and g . if the outputs are activated before t avqv , the data lines will be driven to an indeterminate state until t avqv .ifthead- dress inputs are changed while e and g remain active, output data will remain valid for t axqx (out- put data hold time) but will go indeterminate until the next address access. figure 6. read mode ac waveforms note: we = high. table 7. read mode ac characteristics note: 1. valid for ambient operating temperature: t a =0to70c;v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. c l = 5pf. symbol parameter (1) M48T128Y m48t128v unit C70 C85 min max min max t avav read cycle time 70 85 ns t avqv address valid to output valid 70 85 ns t elqv chip enable low to output valid 70 85 ns t glqv output enable low to output valid 40 55 ns t elqx (2) chip enable low to output transition 5 5 ns t glqx (2) output enable low to output transition 5 5 ns t ehqz (2) chip enable high to output hi-z 25 30 ns t ghqz (2) output enable high to output hi-z 25 30 ns t axqx address transition to output transition 10 5 ns ai01197 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz data out a0-a16 e g dq0-dq7 valid
M48T128Y, m48t128v 8/18 write mode the M48T128Y/v is in the write mode whenever w (write enable) and e (chip enable) are low state after the address inputs are stable. the start of a write is referenced from the latter occurring falling edge of w or e .awriteistermi- nated by the earlier rising edge of w or e . the ad- dresses must be held valid throughout the cycle. e or w must return high for a minimum of t ehax from chip enable or t whax from write enable prior to the initiation of another read or write cycle. data-in must be valid t dvwh prior to the end of write and remain valid for t whdx afterward. g should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on e and g alowonw will disable the outputs t wlqz after w falls. figure 7. write enable controlled, write ac waveform figure 8. chip enable controlled, write ac waveforms ai02382 tavav twhax tdvwh data input a0-a16 e w dq0-dq7 valid tavwh tavel twlwh tavwl twlqz twhdx twhqx ai02383 tavav tehax tdveh a0-a16 e w dq0-dq7 valid taveh tavel tavwl teleh tehdx data input
9/18 M48T128Y, m48t128v table 8. write mode ac characteristics note: 1. valid for ambient operating temperature: t a =0to70c;v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. c l = 5pf. 3. if e goes low simultaneously with w going low, the outputs remain in the high impedance state. symbol parameter (1) M48T128Y m48t128v unit C70 C85 min max min max t avav write cycle time 70 85 ns t av wl address valid to write enable low 0 0 ns t av el address valid to chip enable low 0 0 ns t wlwh write enable pulse width 50 60 ns t eleh chip enable low to chip enable 1 high 55 65 ns t whax write enable high to address transition 5 5 ns t ehax chip enable high to address transition 10 15 ns t dvwh input valid to write enable high 30 35 ns t dveh input valid to chip enable high 30 35 ns t whdx write enable high to input transition 5 5 ns t ehdx chip enable high to input transition 10 15 ns t wlqz (2,3) write enable low to output hi-z 25 30 ns t avwh address valid to write enable high 60 70 ns t ave h address valid to chip enable high 60 70 ns t whqx (2,3) write enable high to output transition 5 5 ns
M48T128Y, m48t128v 10/18 data retention mode with valid v cc applied, the M48T128Y/v operates as a conventional bytewide? static ram. should the supply voltage decay, the ram will au- tomatically power-fail deselect, write protecting it- self when v cc falls within the v pfd (max), v pfd (min) window. all outputs become high imped- ance, and all inputs are treated as don't care. note: a power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the ram's con- tent. at voltages below v pfd (min), the user can be assured the memory will be in a write protected state, provided the v cc fall time is not less than t f . the M48T128Y/v may respond to transient noise spikes on v cc that reach into the deselect window during the time the device is sampling v cc . there- fore, decoupling of the power supply lines is rec- ommended. when v cc drops below v so , the control circuit switches power to the internal battery, preserving data and powering the clock. the internal energy source will maintain data in the M48T128Y/v for an accumulated period of at least 10 years at room temperature. as system power rises above v so , the battery is disconnected, and the power supply is switched to external v cc . deselect continues for t rec after v cc reaches v pfd (max). figure 9. power down/up mode ac waveforms table 9. power down/up ac characteristics note: 1. valid for ambient operating temperature: t a =0to70c;v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. v pfd (max) to v pfd (min) fall time of less than tf may result in deselection/write protection not occurring until 200s after v cc pass- es v pfd (min). 3. v pfd (min) to v ss fall time of less than t fb may cause corruption of ram data. symbol parameter (1) min max unit t f (2) v pfd (max) to v pfd (min) v cc fall time 300 s t fb (3) v pfd (min) to v ss v cc fall time 10 s t r v pfd (min) to v pfd (max) v cc rise time 0s t rb v ss to v pfd (min) v cc rise time 1s t rec v pfd (max) to inputs recognized 40 200 ms ai03612 v cc inputs outputs don't care high-z tf tfb tdr trec trb valid valid recognized recognized v pfd (max) v pfd (min) v ss
11/18 M48T128Y, m48t128v table 10. power down/up trip points dc characteristics note: 1. all voltages referenced to v ss . 2. valid for ambient operating temperature: t a =0to70c;v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 3. at 25c. clock operations reading the clock updates to the tim ekeeper ? registers should be halted before clock data is read to prevent reading data in transition. the biport? time- keeper cells in the ram array are only data reg- isters and not the actual clock counters, so updating the registers can be halted without dis- turbing the clock itself. updating is halted when a '1' is written to the read bit, d6 in the control register (1fff8h). as long as a '1' remains in that position, updating is halted. after a halt is issued, the registers reflect the count; that is, the day, date, and time that were current at the moment the halt command was is- sued. all of the timekeeper registers are updat- ed simultaneously. a halt will not interrupt an update in progress. updating is within a second af- ter the bit is reset to a '0.' setting the clock bit d7 of the control register (1fff8h) is the writebit.settingthewritebittoa'1,'likethe read bit, halts updates to the time keeper reg- isters. the user can then load them with the cor- rect day, date, and time data in 24 hour bcd format (see table 11, page 12). resetting the write bit to a '0' then transfers the values of all time registers 1ffffh-1fff9h to the actual time- keeper counters and allows normal operation to resume. after the write bit is reset, the next clock update will occur one second later. stopping and starting the oscillator the oscillator may be stopped at any time. if the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. the stop bit is located at bit d7 within 1fff9h. setting it to a '1' stops the oscillator. the M48T128Y/v is shipped from stmicroelectronics with the stop bit set to a '1.' when reset to a '0,' the M48T128Y/ v oscillator starts after one second. symbol parameter (1,2) min typ max unit v pfd power-fail deselect voltage M48T128Y 4.1 4.35 4.5 v m48t128v 2.7 2.9 3.0 v v so battery back-up switchover voltage M48T128Y 3.0 v m48t128v v pfd C100mv v t dr (3) expected data retention time 10 years
M48T128Y, m48t128v 12/18 table 11. register map keys: s = sign bit r = read bit w=writebit st = stop bit 0=mustbesetto'0' z = '0' and are read only y='1'or'0' calibrating the clock the M48T128Y/v is driven by a quartz controlled oscillator with a nominal frequency of 32,768hz. the devices are factory calibrated at 25c and tested for accuracy. clock accuracy will not ex- ceed 35 ppm (parts per million) oscillator frequen- cy error at 25c, which equates to about 1.53 minutes per month. when the calibration circuit is properly employed, accuracy improves to better than +1/C2 ppm at 25c. the oscillation rate of crystals changes with temperature (see figure 10, page 13). the M48T128Y/v design employs peri- odic counter correction. the calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 128 stage, as shown in fig- ure 11, page 13. the number of times pulses are blanked (subtract- ed, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the control regis- ter. adding counts speeds the clock up, subtract- ing counts slows the clock down. the calibration bits occupy the five lower order bits (d4-d0) in the control register 1fff8h. these bits can be set to represent any value between 0 and 31 in binary form. bit d5 is a sign bit; '1' indicates positive cal- ibration, '0' indicates negative calibration. calibra- tion occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. if a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is load- ed, the first 12 will be affected, and so on. there- fore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125, 829, 120 actual oscillator cycles, that is +4.068 or C2.034 ppm of adjustment per calibra- tion step in the calibration register. assuming that the oscillator is running at exactly 32,768hz, each of the 31 increments in the calibration byte would represent +10.7 or C5.35 seconds per month which corresponds to a total range of +5.5 or C2.75 minutes per month. one method is available for ascertaining how much calibration a given M48T128Y/v may re- quire. this involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed pe- riod of time. calibration values, including the number of sec- onds lost or gained in a given period, can be found in the stmicroelectronics application note, timekeeper calibration. this allows the designer to give the end user the ability to calibrate the clock as the environment re- quires, even if the final product is packaged in a non-user serviceable enclosure. the designer could provide a simple utility that accesses the calibration byte. for example, a deviation of 21 seconds slow over a period of 30 days would indi- cate a C8 ppm oscillator frequency error, requiring a +2(wr100010) to be loaded into the calibration byte for correction. address data function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 1fffh 10 years year year 00-99 1ffeh 0 0 0 10 m month month 01-12 1ffdh 0 0 10 date date date 01-31 1ffch 0 ft 0 0 0 day day 01-07 1ffbh 0 0 10 hours hours hours 00-23 1ffah 0 10 minutes minutes minutes 00-59 1ff9h st 10 seconds seconds seconds 00-59 1ff8h w r s calibration control
13/18 M48T128Y, m48t128v figure 10. crystal accuracy across temperature figure 11. clock calibration ai02124 -80 -60 -100 -40 -20 0 20 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 d f = -0.038 (t - t 0 ) 2 10% f ppm c 2 t 0 = 25 c ppm c ai00594b normal positive calibration negative calibration
M48T128Y, m48t128v 14/18 v cc noise and negative going transients i cc transients, including those produced by output switching, can produce voltage fluctuations, re- sultinginspikesonthev cc bus. these transients can be reduced if capacitors are used to store en- ergy which stabilizes the v cc bus. the energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. a ceramic by- pass capacitor value of 0.1f (as shown in figure 12) is recommended in order to provide the need- ed filtering. in addition to transients that are caused by normal sram operation, power cycling can generate neg- ative voltage spikes on v cc that drive it to values below v ss by as much as one volt. these negative spikes can cause data corruption in the sram while in battery backup mode. to protect from these voltage spikes, it is recommended to con- nect a schottky diode from v cc to v ss (cathode connected to v cc , anode to v ss ). schottky diode 1n5817 is recommended for through hole and mbrs120t3 is recommended for surface mount. figure 12. supply voltage protection ai02169 v cc 0.1 m f device v cc v ss
15/18 M48T128Y, m48t128v part numbering table 12. ordering information scheme note: 1. contact local st sales office for availability of 3.3v version. for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest you. example: m48t 128y C70 pm 1 tr device type m48t supply voltage and write protect voltage 128y = v cc = 4.5 to 5.5v; v pfd = 4.1 to 4.5v 128v (1) =v cc = 3.0 to 3.6v; v pfd = 2.7 to 3.0v speed C70 = 70ns (128y) C85 = 85ns (128v) package pm = pmdip32 temperature range 1 = 0 to 70c shipping method for soic blank = tubes tr = tape & reel
M48T128Y, m48t128v 16/18 package mechanical information figure 13. pmdip32 C 32-pin plastic module dip, package outline note: drawing is not to scale. table 13. pmdip32 C 32-pin plastic module dip, package mechanical data symb mm inches typ min max typ min max a 9.27 9.52 0.365 0.375 a1 0.38 C 0.015 C b 0.43 0.59 0.017 0.023 c 0.20 0.33 0.008 0.013 d 42.42 43.18 1.670 1.700 e 18.03 18.80 0.710 0.740 e1 2.29 2.79 0.090 0.110 e3 34.29 41.91 1.350 1.650 ea 14.99 16.00 0.590 0.630 l 3.05 3.81 0.120 0.150 s 1.91 2.79 0.075 0.110 n32 32 pmdip a1 a l be1 d e n 1 ea e3 s c
17/18 M48T128Y, m48t128v revision history table 14. document revision history date rev. # revision details june 1998 1.0 first issue 01/31/00 1.1 calibrating the clock paragraph changed 03/30/00 1.2 storage temperature changed (table 2) 07/20/01 2.0 reformatted; temperature information added to tables (table 4, 5, 7, 8, 9, 10) 09/21/01 2.1 corrected speed grade in ordering information 05/23/02 2.2 add countries to disclaimer; add marketing status 08/07/02 2.3 refine marketing status text
M48T128Y, m48t128v 18/18 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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